An MRAM cell typically includes a magnetic storage element, for example, a magnetic tunnel junction (MTJ) device, for storing a bit of information represented by two stable states in which the memory cell can reside. While semiconductor process technology, such as, for example, complementary metal-oxide-semiconductor (CMOS) technology, used to fabricate MRAM cells continues to scale aggressively below 0.18 micrometer (μm) dimensions, conventional MTJ devices often encounter difficulties due, at least in part, to a super-paramagnetic effect. The super-paramagnetic effect generally arises from fundamental principles of thermal dynamics and is related to the total magnetic moment per bit, the switching field, and the temperature of the MTJ device in storage or operation.
When an energy barrier between the two stable states of a given MRAM cell (often defined as a product of the total magnetic moment and the switching field associated with the device) is not much larger than the thermal energy per single degree of freedom kT, where k is Boltzman's constant and T is temperature in degrees Kelvin, the thermal energy alone could spontaneously switch the state of the memory cell without any external excitation (e.g., magnetic field). This may cause the information stored in the MRAM to randomize over time, thus undesirably affecting the data integrity of the MRAM. The requirement of maintaining an adequately large total magnetic moment for a given MRAM cell in order to avoid spontaneous switching is in direct contradiction with the trend to scale down the size of the MRAM cell and switching field.
In order to increase density in an MRAM array, it is known to use a memory cell architecture that comprises more than one magnetic storage element. For example, co-pending U.S. patent application entitled “Magnetic Random Access Memory Cell,” filed on Oct. 22, 2003 and assigned Ser. No. 10/691,300, which is incorporated by reference herein, describes an n-transistor, n-MTJ memory cell providing increased cell density without significantly reducing a lateral size of the MTJ device associated with the memory cell. Conventional multiple-bit memory cell architectures, however, generally exhibit a reduced write margin. This is due, at least in part, to the fact that the region of operation during writing is substantially symmetrical in all four quadrants of a write plane in which the memory cell is written. Consequently, the multiple bits in a given memory cell must share the region of operation with one another.
There exists a need, therefore, for an architecture for implementing a magnetic memory cell which provides increased memory cell density without suffering from one or more of the above-noted deficiencies associated with conventional magnetic memory cells. Moreover, it would be desirable if the improved memory cell architecture was compatible with existing integrated circuit (IC) fabrication process technologies.